Hewlett-Packard Scientists Envision 10-Teraflop Manycore Chip

The architecture, known as Corona, first conceived back in 2008, consists of a 256-core CPU, an optical memory module, integrated nanophotonics and 3D chip stacking employing through-silicon-vias (TSVs). At peak output, Corona should deliver 10 teraflops of performance. That's assuming 16 nm CMOS process technology, which is expected to be on tap by 2017.

The Corona design is aimed squarely at data-intensive types of application, whose speed is limited by the widening gap between CPU performance and available bandwidth to DRAM -- the so-called memory wall. Basically any workload whose data does not fit into processor cache is a candidate. This includes not just traditional big data applications, but also a whole bunch of interesting HPC simulations and analytics codes that have to manipulate large or irregular data sets, and are thus memory-constrained.
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Corona contains 256 cores, each supporting up to four threads simultaneously. The Corona cores themselves are nothing exotic. The HP researchers originally assumed low-power Intel x86 Penryn and Silverthorne CPU core architectures for their design simulations, but presumably ARM or other low-power designs could be substituted.

The processor is divided into 16 quad-core "clusters," with an integrated memory controller on every cluster. The rationale for the hierarchy is to ensure that memory bandwidth grows in concert with the core count and local memory access maintains low latency.

The processor is stacked with the memory controller/L2 cache, the analog electronics and the optical die (which includes on-chip lasers). Everything is hooked together by a 20 TB/sec dense wavelength division multiplexing (DWDM) crossbar, enabling cache coherency between cores, as well as superfast access to that cache.