bios wakeup

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CMOS RAM Bank 1

The first 64 bytes of bank 1 is the same as bank 0; for a definition of these bytes, refer to CMOS RAM--Bank 0

Note:
Access to the two banks in CMOS RAM is controlled by the bank-control bit in Status Register A (see Status Register A (Hex 00A))

System Number (Hex 40-47F)
Century Byte (Hex 48)
Wake-up Alarm Date (Hex 49)
Extended Control Register A (Hex 4A)
Extended Control Register B (Hex 4B)
Reserved (Hex 4C-7F)

System Number (Hex 40-47F)
These bytes are read-only and contain a unique 64-bit system identifier number. The identifier is divided into three parts. The first byte is the version number for the real-time clock chip. The next six bytes (index 41 through 46) contain a system-unique identifier. The last byte is the CRC for the first seven bytes. The system identifier for the Server is FFFFF4h.

Century Byte (Hex 48)
This byte is the century and is coded in the same format (binary or BAD) as specified by the date-mode bit. The range of values is from century 00 to century 99.

Wake-up Alarm Date (Hex 49)
This byte contains the alarm setting for a wake-up call to the system. When the date in the real-time clock matches this setting, the Server 95 is automatically powered-on if the alarm is enabled (see'Extended Control Register B (Hex 4B)').

Extended Control Register A (Hex 4A)
This read/write register controls security and unattended-power features of the Server 95.
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----+-----+-----+-----+-----+-----+-----|
| BAT | BSY | R | R | PAC | TF | WF | KF |
+-----------------------------------------------+
BAT: Battery status
BSY: Clock update in progress
PAC: Power active control
TF: Tamper evident status
WF: Wake-up alarm status
KF: Kickstart status
R: Reserved

BAT The battery-status bit is a read-only bit that indicates the output reading of the battery. When the bit is 1, the output is active.
If the battery is enabled, this bit indicates whether the battery is operating correctly. If the battery is disabled, this bit is always 0.

BSY The clock-update-in-progress bit is a read-only bit; the hardware sets this bit to 1 to indicate that the time and date registers are being updated. The bit is set 125 microseconds before the update cycle; it is reset at the end of the update cycle.

PAC The power-active-control bit controls the power supply when the power switch is in the standby mode. The kickstart feature or the wake-up alarm set this bit to 0 when they power-on the system. Setting this bit to 1 while the power switch is in the standby mode turns the system power off.

Note: To determine whether the power switch is in the power-on mode or the standby mode, see Operator Panel Information.

When system is powered-on with the power switch, POST sets this bit to 1. While the power switch is in the power-on mode, this bit has no effect on the system operation.

TF The tamper-evident-status bit indicates whether the covers have been breached, causing CMOS RAM to be erased and an interrupt to be generated. Setting this bit to 0 clears the interrupt. (The clear-RAM-enable bit must be set to 1 for this status bit to be set to 1).

WF The wakeup-alarm-status bit indicates whether the system has been powered-on because of a wakeup alarm. When the bit is 1, the time matched the alarm setting, the real-time clock has generated a power-on request and a system interrupt. Setting this bit to 0 clears the interrupt.

Note: This bit and the kickstart-status bit are valid only if the system was not powered-on with the power switch. To determine whether the power switch is in the power-on mode or the standby mode, see Operator Panel Information.

KF The kickstart-status bit indicates whether the system has been powered-on because of the kickstart feature. When the bit is 1, the kickstart feature has generated a power-on request and a system interrupt. Setting this bit to 0 clears the interrupt.

Extended Control Register B (Hex 4B)
This read/write register controls security and unattended-power features of the Server 95.
+--------------------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|------+------+------+------+------+-------+------+------|
| EXT | R | R | CLR | R | TIE | WE | KE |
+--------------------------------------------------------+
EXT: External battery enable
CLR: Clear RAM enable
WE: Wake-up alarm enable
KE: Kickstart enable
R: Reserved

EXT The external-battery-enable bit controls the source of the battery backup to the real-time clock chip. When the bit is set to 1, the chip uses an external battery source.

CLR The clear-RAM-enable bit controls the tamper evident logic. When this bit is set to 1, the configuration information in CMOS RAM is erased when the covers are breached. When this bit is 0, CMOS RAM is not erased.

TE The tamper-evident-interrupt-enable bit determines whether an interrupt is generated if the covers have been breached. When the bit is set to 1, an interrupt is generated after CMOS RAM has been cleared.

WE The wakeup-alarm-enable bit controls whether the real-time clock generates a wakeup alarm when the time matches the wakeup-alarm setting. When the bit is set to 1 and an alarm occurs, the system is powered-on and an interrupt is generated.

KE The kickstart-enable bit controls whether serial port A generates power-on request when it receives an incoming call. When the bit is set to 1 and a call is received, the serial port causes the system to power-on, and an interrupt is generated.

Reserved (Hex 4C-7F)
These bytes are reserved.

CMOS RAM Bank 0

Real-Time Clock Bytes (Hex 000-00D)
Status Register A (Hex 00A)
Status Register B (Hex 00B)
Status Register C (Hex 00C)
Status Register D (Hex 00D)

Real-Time Clock Bytes (Hex 000-00D)
Bit definitions and addresses for the Real-Time Clock bytes are shown in the following figure.

Real-Time Clock Bytes (Hex 000-00D)
ADDRESS
(HEX) FUNCTION
00 Seconds
01 Second alarm
02 Minutes
03 Minute alarm
04 Hours
05 Hour alarm
06 Day of week
07 Date of month
08 Month
09 Year
0A Status Register A
0B Status Register B
0C Status Register C
0D Status Register D

Note: The Setup program initializes Status Register A and Status Register B when the time and date are set. Interrupt 1Ah is the BIOS interface that is used to read and set the time and date; it initializes the registers in the same way that the Setup program does.

Status Register A (Hex 00A)
+--------------------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|------+--------------+-------+--------------------------|
| UIP | SDIV | BC | Rate |
+--------------------------------------------------------+
UIP: Update in progress
SDIV: Select divider
BC: Bank control
RATE: Rate select

UIP The update-in-progress bit is a read-only bit that indicates when the time and date registers are being updated. When the bit is 1, an update is in progress. When it is set to 0, the current date and time can be read.

SDIV This two-bit field specifies the time-base frequency is being used. The system initializes these bits to binary 01, which selects a 32.768-kHz time base. This is the only value that is supported by the system for proper timekeeping.

BC The bank-control bit selects the bank of CMOS RAM that is accessed through the real-time clock. When this bit is set to 0, bank 0 is accessed through the RTC Data register. When this bit is set to 1, bank 1 is accessed.

Rate This four-bit field selects the divider output frequency. The system initializes these bits to a binary 0110, which selects a 1.024-kHz square-wave output frequency and a 976.562-microsecond periodic interrupt rate.

Status Register B (Hex 00B)
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----+-----+-----+-----+-----+-----+-----|
| SET | PIE | AIE | UIE | SQW | DM |24/12| DSE |
+-----------------------------------------------+
SET: Set clock
PIE: Enable periodic int
AIE: Enable alarm int
UIE: Enable update-ended int
SQW: Enable square-wave
DM: Date mode
24/12: 24-Hour mode
DSE: Enable daylight saving

SET When this bit is set to 0, the clock updates the cycle normally by advancing the count at a rate of one per second. When this bit is set to 1, the clock immediately ends any update cycle in progress, and the program can initialize the 14 time bytes without updates occurring until this bit is reset to 0.

PIE The period-interrupt-enable bit enables an interrupt to occur at a rate that is specified by the rate and divider bits in Status Register A. When this bit is set to 1, the interrupt is enabled. The system initializes this bit to 0.

AIE The alarm-interrupt-enable bit enables an interrupt to occur when the time matches the values specified in the alarm bytes. When this bit is set to 1, the alarm interrupt is enabled. The system initializes this bit to 0.

UIE The update-interrupt-enable bit enables an interrupt t occur when the clock has completed an update cycle. When this bit is set to 1, the update-ended interrupt is enabled. The system initializes this bit to 0.

SQW The square-wave-enable bit determines whether the square-wave generator is enabled. When this bit is set to 1, the generator is enabled and uses the frequency specified by the rate-selection bits in Status Register A. The system initializes this bit to 0.

DM The date-mode bit specifies whether the internal counters use binary-coded-decimal (BCD) or binary format for time-and-date calendar updates. When this bit is set to 1, the binary format is used. The system initializes this bit to 0.

24/12 The 24/12-hour bit specifies whether the hour byte is in 12-hour or 24-hour mode. When this bit is set to 1, the 24-hour mode is used. The system initializes this bit to 1.

DSE When this bit is set to 1, the daylight-saving-time mode is enabled. When this bit is set to 0, the daylight-saving-time mode is disabled, and the clock reverts to standard time. The system initializes this bit to 0.

Status Register C (Hex 00C)
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----+-----+-----+-----------------------|
| IRQ | PF | AF | UF | Reserved |
+-----------------------------------------------+
IRQ: Interrupt-request
PF: Periodic-interrupt
AF: Alarm-interrupt
UF: Update-ended interrupt

Note: Interrupts are enabled by bits 6, 5, and 4 in Status Register B and Extended Control Register A.

IRQ The interrupt-pending bit indicates that the real-time clock has a system interrupt pending. When this bit is 1, the real-time clock has generated a system interrupt. Bits 6, 5, and 4 in this register and bits 2 through 0 in Extended Control Register A indicate the cause of the interrupt.

Note: The interrupt-pending bit is normally reset when this register is read; however, for interrupts in Extended Control Register A, the interrupt must first be cleared by resetting the corresponding bit to 0 (see Extended Control Register A (Hex 4A)).

PF When this bit is 1, a periodic interrupt occurred.
AF When this bit is 1, an alarm interrupt occurred.
UF When this bit is 1, an update-ended interrupt occurred.

Status Register D (Hex 00D)
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----------------------------------------|
| VM | Reserved |
+-----------------------------------------------+
VM: Valid RAM

VM The valid-RAM bit is a read-only bit that indicates whether the contents of CMOS RAM is good. When this bit is 1, the data of CMOS RAM is considered valid; when the bit is 0, the data in CMOS is no longer valid.
CMOS RAM

The bit definitions for the CMOS RAM configuration bytes are:

Diagnostic Status Byte (Hex 00E)
Shutdown Status Byte (Hex 00F)
Diskette Drive Type Byte (Hex 010)
First Fixed Disk Drive Type Byte (Hex 011)
Second Fixed Disk Drive Type Byte (Hex 011)
Reserved Bytes (Hex 012, 013)
Equipment Byte (Hex 014)
Low and High Base Memory Bytes (Hex 015 and 016)
Low and High Expansion Memory Bytes (Hex 017 and 018)
Reserved Bytes (Hex 019 through 031)
Configuration CRC Bytes (Hex 032 and 033)
Reserved Byte (Hex 034)
Low and High Usable Memory Bytes (Hex 035 and 036)
Date-Century Byte (Hex 037)
Reserved Bytes (Hex 038-04F)

Diagnostic Status Byte (Hex 00E)

+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----+-----+-----+-----+-----+-----+-----|
| PWR | SUM | CFG | SIZ | FDC | TS | R | R |
+-----------------------------------------------+
PWR: Clock power
SUM: Checksum status
CFG: Configuration error
SIZ: Memory-size miscompare
FDC: Fixed disk C status
TS: Time status
R: Reserved

PWR When the clock-power bit is 1, the real-time clock has lost power.

SUM When the checksum-error bit is 1, the checksum is incorrect.

CFG When the configuration-error bit is 1, the power-on check of the Equipment byte (hex 014) failed.

SIZ When the memory-size-miscompare bit is 1, the memory size does not match the configuration information in CMOS RAM.

FDC When the fixed-disk-C bit is 1, the controller or hard disk drive failed to initialize.

TS When the time-status bit is 1, the time is not valid.

Shutdown Status Byte (Hex 00F)
This byte is defined by the power-on diagnostic programs.

Diskette Drive Type Byte (Hex 010)
This byte indicates the type of diskette drive that is installed.
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------------------+-----------------------|
| Disk A | Disk B |
+-----------------------------------------------+
These two 4-bits fields indicate the drive type of the first and second diskette drives.

Diskette Drive Type
BITS
7 6 5 4 DESCRIPTION
0 0 0 0 No drive present
0 0 0 1 5.25-inch, 360KB diskette drive
0 0 1 0 5.25-inch, 1.2MB diskette drive
0 1 0 0 3.5-inch, 1.44MB diskette drive
0 1 1 0 3.5-inch, 2.88MB diskette drive
NOTE: Combinations that are not shown are reserved.

First Fixed Disk Drive Type Byte (Hex 011)
This byte defines the type of the fixed disk drive that is installed. A value of hex 00 indicates that no fixed disk drive is installed.

Second Fixed Disk Drive Type Byte (Hex 011)
This byte defines the type of the fixed disk drive that is installed. A value of hex 00 indicates that no fixed disk drive is installed.

Reserved Bytes (Hex 012, 013)
These bytes are reserved.

Equipment Byte (Hex 014)
This byte defines the basic equipment in the system for the power-on diagnostic tests.
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------+-----------+-----+-----+-----+-----|
| # DD | Display | R | R | CP | DDA |
+-----------------------------------------------+
# DD: Number of diskette drives
DISPLAY: Display operating mode
CP: Math coprocessor present
DDA: Diskette drive A present

# DD These bits represent the number of diskette drives installed other than the drive A.

Installed Diskette Drives

BITS
7 6 NUMBER OF DISKETTE DRIVES
0 0 No additional diskette drives
0 1 One additional diskette drive
1 0 Two additional diskette drives
1 1 Reserved

Display These bits indicate the operating mode of the display that is attached to the video connector.

Display Operating Mode Bits

BITS DISPLAY OPERATING MODE
5 4
0 0 Reserved
0 1 40-Column mode
1 0 80-Column mode
1 1 Monochrome mode

CP When this bit is 1, the math coprocessor function is present.
DDA When this bit is 1, diskette drive A is present.

Low and High Base Memory Bytes (Hex 015 and 016)
These bytes define the amount of memory below the 640KB address space.
The value of these bytes indicates the number of 1KB blocks of base memory. For example, hex 0280 indicates 640KB of base memory. The low byte is hex 015; the high byte is hex 016.

Low and High Expansion Memory Bytes (Hex 017 and 018)
These bytes define the amount of memory above the 1MB address space.
The value of these bytes indicates the number of 1KB blocks of expansion memory. For example, hex 0800 indicates 2048KB of expansion memory. The low byte is hex 017; the high byte is hex 018.

Reserved Bytes (Hex 019 through 031)
These bytes are reserved.

Configuration CRC Bytes (Hex 032 and 033)
These bytes contain the cyclic-redundancy-check (CRC) data for bytes hex 010 through 031 of the 64-byte CMOS RAM. The low byte is hex 033; the high byte is hex 032.

Reserved Byte (Hex 034)
These bytes are reserved.

Low and High Usable Memory Bytes (Hex 035 and 036)
These bytes define the total amount of contiguous usable memory from 1MB to 16MB. The value of these bytes indicates the number of 1KB blocks of usable memory. For example, hex 0800 indicates 2048KB of contiguous usable memory. The low byte is hex 035; the high byte is hex 036.

Date-Century Byte (Hex 037)
Bits 7 through 0 of this byte contain the BCD value for the century.

Reserved Bytes (Hex 038-04F)
These bytes are reserved.
CMOS Registers

The CMOS RAM data area consists of two banks of 128 bytes. The first 64 bytes in both bank are the same and contain clock and calendar information. The second 64 bytes in bank 1 control security and system start-up features.

Note: Access to the two banks in CMOS RAM is controlled by the bank-control bit in Status Register A (see Status Register A (Hex 00A)).
The following figure shows the addresses and definition for the first 64 bytes of RT/CMOS RAM.

RAM Address Map
RT/CMOS
ADDRESS
(HEX) RT/CMOS RAM BYTES
000-00D Real-Time Clock bytes
00E Diagnostic Status byte
00F Shutdown Status byte
010 Diskette Drive Type byte
011 First Fixed Disk Drive Type byte
012, 013 Reserved
014 Equipment byte
015, 016 Low and high Base Memory bytes
017, 018 Low and high Expansion Memory bytes
019-031 Reserved
034 Reserved
035, 036 Low and high usable memory above 1MB
037 Date Century byte
038-07F Reserved

Warning:
The operation that follows a write operation to address hex 0070 must read from address hex 0071; otherwise intermittent malfunctions and unreliable operation of the RT/CMOS RAM can occur.

CMOS RAM Bank 0
000-00D Real-Time Clock Bytes
00A Status Register A Timer Related
00B Status Register B Date and Alarm Related
00C Status Register C Interrupt Related
00D Status Register D CMOS Valid Byte

CMOS RAM Configuration
00E Diagnostic Status Byte Configuration Related
00F Shutdown Status Byte Set by power-on diagnostics
010 FD Type Byte Type of Floppy installed
011 1st Fixed Disk Drive Type Byte Type HD installed
011 2nd Fixed Disk Drive Type Byte Type HD installed
012,013 Reserved Bytes
014 Equipment Byte #FDs, Display, Co-pro, A: present
015,016 Low and High Base Memory Bytes Memory <640KB
017,018 Low and High Expansion Memory Bytes Memory >1MB
019-031 Reserved Bytes
032,033 Configuration CRC Bytes CRC data for RTC CMOS
034 Reserved Byte
035,036 Low and High Usable Memory Bytes Memory 1-16MB
037 Date-Century Byte BCD Value for century
038-04F Reserved Bytes

CMOS RAM Bank 1
40-47F System Number System Identifier
48 Century Byte BCD Value for Cenuty
49 Wake-up Alarm Date Date set for Power-On
4A Extended Control Register A Security and power-on
4B Extended Control Register B Security and power-on
4C-7F Reserved