Bus clear
In the unlikely event where the clock (SCL) is stuck LOW, the preferential procedure is to
reset the bus using the HW reset signal if your I2C devices have HW reset inputs. If the
I2C devices do not have HW reset inputs, cycle power to the devices to activate the
mandatory internal Power-On Reset (POR) circuit.
If the data line (SDA) is stuck LOW, the master should send nine clock pulses. The device
that held the bus LOW should release it sometime within those nine clocks. If not, then
use the HW reset or cycle power to clear the bus.
és
Unresponsive slave reset
In the unlikely event where the slave becomes unresponsive (for example, determined
through external feedback, not through UFm I2C-bus), the preferential procedure is to
reset the slave by using the software reset command or the hardware reset signal. If the
slaves do not support these features, then cycle power to the devices to activate the
mandatory internal Power-On Reset (POR) circuit.
Legalábbis az NXP szerint. ;)
A 0Hz azt jelenti, hogy a timeout nem értelmezett.